A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

AuthID
 P-00A-4B4
3
Author(s)
Tipo de Documento
Article
Year published
2015
Publicado
in ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, ISSN: 1936-7406
Volume: 7, Número: 4, Páginas: 29:1-29:20 (20)
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Dblp®/pt/publications/view/332132
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Publication Identifiers
DBLP: journals/trets/PaulinoFC15
SCOPUS: 2-s2.0-84911387509
Wos: WOS:000350529900002
Source Identifiers
ISSN: 1936-7406
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