Fernando Manuel Duarte Gonçalves


AuthID: R-000-51G

Confirmed Publications: 34



21
TITLE: Defect-oriented sampling of non-equally probable faults in VLSI systems  Full Text
AUTHORS: Goncalves, FM ; Teixeira, JP ;
PUBLISHED: 1999, SOURCE: Proceedings of the 1998 16th IEEE VLSI Test Symposium, (VTS 98): Test Innovations for Highly Complex, High Speed, Deep Submicron IC's in JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, VOLUME: 15, ISSUE: 1-2
INDEXED IN: Scopus WOS CrossRef: 4
IN MY: ORCID
22
TITLE: Defect-Oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique  Full Text
AUTHORS: Santos, MB ; Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1999, SOURCE: 17th IEEE Very Large Scale Intergration Test Symposium in 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
23
TITLE: Defect-oriented testing of analogue and mixed signal ICs
AUTHORS: Santos, MB ; Goncalves, FM ; Ohletz, M; Teixeira, JP ;
PUBLISHED: 1998, SOURCE: Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
INDEXED IN: Scopus CrossRef: 5
IN MY: ORCID
24
TITLE: Detect-oriented test quality assessment using fault sampling and simulation  Full Text
AUTHORS: Goncalves, FM ; Santos, MB ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1998, SOURCE: International Test Conference 1998 in INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
25
TITLE: Sampling techniques of non-equally probable faults in VLSI systems  Full Text
AUTHORS: Goncalves, FM ; Teixeira, JP ;
PUBLISHED: 1998, SOURCE: 16th IEEE VLSI Symposium in 16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
26
TITLE: Realistic fault extraction for high-quality design and test of VLSI systems
AUTHORS: Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1997, SOURCE: 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems in 1997 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
27
TITLE: Defect level evaluation in an IC design environment  Full Text
AUTHORS: deSousa, JT; Goncalves, FM ; Teixeira, JP; Marzocca, C; Corsi, F; Williams, TW;
PUBLISHED: 1996, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 15, ISSUE: 10
INDEXED IN: Scopus WOS
IN MY: ORCID
28
TITLE: Integrated approach for circuit and fault extraction of VLSI circuits
AUTHORS: Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1996, SOURCE: 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems in 1996 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
29
TITLE: Fault modeling and defect level projections in digital ICs
AUTHORS: Sousa, JT; Goncalves, FM ; Teixeira, JP ; Williams, TW;
PUBLISHED: 1994, SOURCE: Proceedings of the European Design and Test Conference in Proceedings of the European Design and Test Conference
INDEXED IN: Scopus
IN MY: ORCID
30
TITLE: On the analysis of routing, cells and adjacency faults in CMOS digital circuits  Full Text
AUTHORS: Casimiro, AP; Santos, MB ; Goncalves, F ; Teixeira, JP ;
PUBLISHED: 1994, SOURCE: Proceedings of the 1994 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems in IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
INDEXED IN: Scopus
IN MY: ORCID
Page 3 of 4. Total results: 34.

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