Isabel Maria Silva Nobre Parreira Cacho Teixeira


AuthID: R-000-6DS

Confirmed Publications: 98



81
TITLE: Metrics and criteria for quality assessment of testable Hw Sw systems architectures  Full Text
AUTHORS: Dias, OP; Teixeira, IC ; Teixeira, JP;
PUBLISHED: 1999, SOURCE: JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, VOLUME: 14, ISSUE: 1-2
INDEXED IN: Scopus WOS CrossRef: 14
IN MY: ORCID
82
TITLE: Detect-oriented test quality assessment using fault sampling and simulation  Full Text
AUTHORS: Goncalves, FM ; Santos, MB ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1998, SOURCE: International Test Conference 1998 in INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
83
TITLE: Realistic fault extraction for high-quality design and test of VLSI systems
AUTHORS: Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1997, SOURCE: 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems in 1997 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
84
TITLE: HW/SW specification using OOM techniques  Full Text
AUTHORS: Calha, M; Teixeira, JP ; Teixeira, IC ;
PUBLISHED: 1996, SOURCE: 7th IEEE International Workshop on Rapid System Prototyping - Shortening the Path from Specification to Prototype in SEVENTH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS: SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
85
TITLE: Integrated approach for circuit and fault extraction of VLSI circuits
AUTHORS: Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1996, SOURCE: 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems in 1996 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
86
TITLE: Test preparation for high coverage of physical defects in CMOS digital ICs
AUTHORS: Santos, MB ; Simoes, M; Teixeira, I ; Teixeira, JP ;
PUBLISHED: 1995, SOURCE: Proceedings of the 13th IEEE VLSI Test Symposium in Proceedings of the IEEE VLSI Test Symposium
INDEXED IN: Scopus
IN MY: ORCID
87
TITLE: TEST PREPARATION METHODOLOGY FOR HIGH COVERAGE OF PHYSICAL DEFECTS IN CMOS DIGITAL ICS  Full Text
AUTHORS: SANTOS, MB ; SIMOES, M; TEIXEIRA, I ; TEIXEIRA, JP ;
PUBLISHED: 1995, SOURCE: European Design and Test Conference (ED&TC 1995) in EUROPEAN DESIGN AND TEST CONFERENCE - ED&TC 1995, PROCEEDINGS
INDEXED IN: WOS
88
TITLE: Digital system for a static electric current meter
AUTHORS: Barbosa, J; Cruz, C; Nicolau, P; Pinto, C; Teixeira, I ;
PUBLISHED: 1992, SOURCE: Proceedings Euro ASIC '92 in EURO ASIC '92
INDEXED IN: Scopus
IN MY: ORCID
89
TITLE: ON THE DESIGN OF A HIGHLY TESTABLE CELL LIBRARY
AUTHORS: SARAIVA, M; SANTOS, MB ; CASIMIRO, AP; TEIXEIRA, IM ; TEIXEIRA, JP ;
PUBLISHED: 1992, SOURCE: 18TH SYMP ON MICROPROCESSING AND MICROPROGRAMMING ( EUROMICRO-92 ) : SOFTWARE AND HARDWARE : SPECIFICATION AND DESIGN in MICROPROCESSING AND MICROPROGRAMMING, VOLUME: 35, ISSUE: 1-5
INDEXED IN: Scopus WOS
IN MY: ORCID
90
TITLE: Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part I  Full Text
AUTHORS: Bafleur, M; Buxo, J; Teixeira, JP ; Teixeira, IC ;
PUBLISHED: 1992, SOURCE: Microelectronics Journal, VOLUME: 23, ISSUE: 8
INDEXED IN: Scopus
IN MY: ORCID
Page 9 of 10. Total results: 98.

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