João Paulo Cacho Teixeira


AuthID: R-000-7A4

Confirmed Publications: 110



91
TITLE: HW/SW specification using OOM techniques  Full Text
AUTHORS: Calha, M; Teixeira, JP ; Teixeira, IC ;
PUBLISHED: 1996, SOURCE: 7th IEEE International Workshop on Rapid System Prototyping - Shortening the Path from Specification to Prototype in SEVENTH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS: SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
92
TITLE: Integrated approach for circuit and fault extraction of VLSI circuits
AUTHORS: Goncalves, FM ; Teixeira, IC ; Teixeira, JP ;
PUBLISHED: 1996, SOURCE: 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems in 1996 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
93
TITLE: VHDL fault simulation for defect-oriented test and diagnosis of digital ICs
AUTHORS: Celeiro, F; Dias, L; Ferreira, J; Santos, MB; Teixeira, JP ;
PUBLISHED: 1996, SOURCE: European Design Automation Conference (EURO-DAC 96), with EURO-VHDL 96 and Exhibition in EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS
INDEXED IN: Scopus WOS
IN MY: ORCID
94
TITLE: Test preparation for high coverage of physical defects in CMOS digital ICs
AUTHORS: Santos, MB ; Simoes, M; Teixeira, I ; Teixeira, JP ;
PUBLISHED: 1995, SOURCE: Proceedings of the 13th IEEE VLSI Test Symposium in Proceedings of the IEEE VLSI Test Symposium
INDEXED IN: Scopus
IN MY: ORCID
95
TITLE: TEST PREPARATION METHODOLOGY FOR HIGH COVERAGE OF PHYSICAL DEFECTS IN CMOS DIGITAL ICS  Full Text
AUTHORS: SANTOS, MB ; SIMOES, M; TEIXEIRA, I ; TEIXEIRA, JP ;
PUBLISHED: 1995, SOURCE: European Design and Test Conference (ED&TC 1995) in EUROPEAN DESIGN AND TEST CONFERENCE - ED&TC 1995, PROCEEDINGS
INDEXED IN: WOS
96
TITLE: Fault modeling and defect level projections in digital ICs
AUTHORS: Sousa, JT; Goncalves, FM ; Teixeira, JP ; Williams, TW;
PUBLISHED: 1994, SOURCE: Proceedings of the European Design and Test Conference in Proceedings of the European Design and Test Conference
INDEXED IN: Scopus
IN MY: ORCID
97
TITLE: On the analysis of routing, cells and adjacency faults in CMOS digital circuits  Full Text
AUTHORS: Casimiro, AP; Santos, MB ; Goncalves, F ; Teixeira, JP ;
PUBLISHED: 1994, SOURCE: Proceedings of the 1994 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems in IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
INDEXED IN: Scopus
IN MY: ORCID
98
TITLE: IC defects-based testability analysis
AUTHORS: Sousa, JJT; Goncalves, FM ; Teixeira, JP ;
PUBLISHED: 1992, SOURCE: Proceedings of the International Test Conference 1991 in Digest of Papers - International Test Conference
INDEXED IN: Scopus
IN MY: ORCID
99
TITLE: Layout-level techniques for testability improvement of MOS physical designs
AUTHORS: Santos, MB ; Goncalves, FM ; Sousa, JJT; Teixeira, JP ;
PUBLISHED: 1992, SOURCE: Proceedings of the 6th Mediterranean Electrotechnical Conference - Melecon '91 in 6th Mediterranean Electrotechnical Conference
INDEXED IN: Scopus
IN MY: ORCID
100
TITLE: ON THE DESIGN OF A HIGHLY TESTABLE CELL LIBRARY
AUTHORS: SARAIVA, M; SANTOS, MB ; CASIMIRO, AP; TEIXEIRA, IM ; TEIXEIRA, JP ;
PUBLISHED: 1992, SOURCE: 18TH SYMP ON MICROPROCESSING AND MICROPROGRAMMING ( EUROMICRO-92 ) : SOFTWARE AND HARDWARE : SPECIFICATION AND DESIGN in MICROPROCESSING AND MICROPROGRAMMING, VOLUME: 35, ISSUE: 1-5
INDEXED IN: Scopus WOS
IN MY: ORCID
Page 10 of 11. Total results: 110.

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