51
TÍTULO: Self-checking and fault tolerance quality assessment using Fault Sampling
AUTORES: Goncalves, FM; Santos, MB; Teixeira, IC; Teixeira, JP;
PUBLICAÇÃO: 2002, FONTE: 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems in 17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, VOLUME: 2002-January
INDEXADO EM: Scopus WOS CrossRef
52
TÍTULO: RTL design validation, DFT and test pattern generation for high defects coverage
AUTORES: Santos, MB; Goncalves, FM; Teixeira, IC; Teixeira, JP;
PUBLICAÇÃO: 2001, FONTE: IEEE European Test Workshop (ETW 01) in ETW 2001: IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS
INDEXADO EM: WOS
53
TÍTULO: Design and test of certifiable ASICs for safety-critical gas burners control
AUTORES: Goncalves, FM; Santos, MB; Teixeira, IC; Teixeira, JP;
PUBLICAÇÃO: 2001, FONTE: 7th IEEE International On-Line Testing Workshop in SEVENTH IEEE INTERNATIONAL ON-LINE TESTING WORKSHOP, PROCEEDINGS
INDEXADO EM: WOS
54
TÍTULO: RTL-based functional test generation for high defects coverage in digital SOCs
AUTORES: Santos, MB; Goncalves, FM; Teixeira, IC; Teixeira, JP;
PUBLICAÇÃO: 2000, FONTE: IEEE European Test Workshop in IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS
INDEXADO EM: WOS
55
TÍTULO: Testability issues in the CMS ECAL upper-level readout and trigger system
AUTORES: Almeida, CB; Teixeira, IC; Teixeira, JP; Varela, J; Augusto, J ; Santos, M; Cardoso, N;
PUBLICAÇÃO: 1999, FONTE: 5th Workshop on Electronics for LHC Experiments in PROCEEDINGS OF THE FIFTH WORKSHOP ON ELECTRONICS FOR LHC EXPERIMENTS
INDEXADO EM: WOS
56
TÍTULO: Low-energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity
AUTORES: Girard, P; Guiller, L; Figueras, J; Manich, S; Teixeira, P; Santos, M;
PUBLICAÇÃO: 1999, FONTE: 1999 IEEE International Symposium on Circuits and Systems (ISCAS 99) in ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI
INDEXADO EM: WOS
57
TÍTULO: VHDL fault simulation for defect-oriented test and diagnosis of digital ICs
AUTORES: Celeiro, F; Dias, L; Ferreira, J; Santos, MB; Teixeira, JP ;
PUBLICAÇÃO: 1996, FONTE: European Design Automation Conference (EURO-DAC 96), with EURO-VHDL 96 and Exhibition in EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS
INDEXADO EM: Scopus WOS
58
TÍTULO: Defect-oriented IC test and diagnosis using VHDL fault simulation  Full Text
AUTORES: Celeiro, F; Dias, L; Ferreira, J; Santos, MB; Teixeira, JP ;
PUBLICAÇÃO: 1996, FONTE: 1996 International Test Conference (ITC 1996) - Test and Design Validity in INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS
INDEXADO EM: Scopus WOS
59
TÍTULO: BACK ANNOTATION OF PHYSICAL DEFECTS INTO GATE-LEVEL, REALISTIC FAULTS IN DIGITAL ICS
AUTORES: CALHA, M; SANTOS, M; GONCALVES, F; TEIXEIRA, I; TEIXEIRA, JP;
PUBLICAÇÃO: 1994, FONTE: International Test Conference 1994 (ITC 94) - TEST; The Next 25-Years in INTERNATIONAL TEST CONFERENCE 1994, PROCEEDINGS
INDEXADO EM: WOS
60
TÍTULO: PHYSICAL DFT FOR HIGH COVERAGE OF REALISTIC FAULTS
AUTORES: SARAIVA, M; CASIMIRO, P; SANTOS, M; SOUSA, JT; GONCALVES, F; TEIXEIRA, I; TEIXEIRA, JP;
PUBLICAÇÃO: 1992, FONTE: 1992 INTERNATIONAL TEST CONF ON DISCOVER THE NEW WORLD OF TEST AND DESIGN in INTERNATIONAL TEST CONFERENCE 1992 : PROCEEDINGS: DISCOVER THE NEW WORLD OF TEST AND DESIGN
INDEXADO EM: WOS
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